1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of manufacturing a semiconductor device in which a barrier layer of a wiring structure has improved adhesion to an insulation layer, and a semiconductor device manufactured by the same method.
2. Description of the Related Art
Nowadays, as semiconductor devices are becoming highly integrated, sizes of source/drain regions and widths of gate electrodes and metal wiring in semiconductor devices are being rapidly reduced. Particularly, the small widths of the metal wiring can cause a rapid increase of an aspect ratio of a contact hole or a via hole, and thus there are difficulties in filling up the contact hole or the via hole by a conventional deposition process. For that reason, a planarization process has recently been introduced for formation of the metal wiring in a semiconductor device. According to such a process: a metal layer is formed on an insulation interlayer to a sufficient thickness to fill up the contact hole or the via hole by a conventional deposition process, and then the metal layer is planarized by the planarization process until a top surface of the insulation interlayer is exposed. As a result, only the metal layer remains in the contact hole or the via hole after the planarization process, thereby forming the metal wiring structure for a semiconductor device. Recently, there has been a strong tendency to form a metal plug as the contact plug in place of a conventional polysilicon plug. Particularly, when a metal plug is used as the via plug, the via plug generally comprises the same metal as the metal wiring, and thus there is an advantage in that the metal wiring and the via plug are formed in the same process.
When a plug or a wiring comprises a metal, a barrier layer along an inner surface of the contact hole or the via hole is usually required to prevent damage to underlying structures arranged under the insulation interlayer in a process for formation of the plug or the wiring. Tungsten (W) has been most widely used in a deposition process for forming the plug or the wiring to facilitate a process for a deposition process and due to its relatively low electrical resistance. However, tungsten has many disadvantages in a formation process of the plug or the wiring in that a tungsten layer can have difficulty in adhering to an oxide layer and source gases in a deposition process for the plug or the wiring can cause damage to the inner surface of the contact hole or the via hole.
In order to overcome the above disadvantages of the tungsten plug or the tungsten wiring, the barrier layer usually includes a glue layer along the inner surface of the contact hole or the via hole and an anti-diffusion layer on the glue layer. The anti-diffusion layer on the glue layer can prevent diffusion of the source gases, such as fluorine (F) ions and the glue layer on the inner surface of the hole can reduce contact resistance of the plug or wiring in the contact hole or the via hole.
The anti-diffusion layer on the glue layer is finally transformed into a portion of the plug or the wiring, and thus needs to satisfy requirements of high uniformity and low contact resistance. That is, the anti-diffusion layer is to be uniformly and evenly formed on the inner surface of a small space, such as the contact hole or the via hole, and is to be formed to have as small a thickness as possible to minimize the contact electrical resistance between the anti-diffusion layer and the metal plug. For the above requirements, a tungsten layer is usually used as the glue layer, and a tungsten nitride (WN) layer is frequently used as the anti-diffusion layer.
The contact hole or the via hole is formed in the insulation interlayer that usually comprises an oxide, and the barrier is formed on the inner surface of the contact hole or the via hole in such a configuration that a first tungsten layer is formed on the inner surface of the hole and a tungsten nitride layer is formed on the first tungsten layer. Then, a second tungsten layer is formed on the barrier layer to a thickness sufficient to fill up the hole, and a planarization process is performed on the second tungsten layer until a top surface of the insulation interlayer is exposed. Accordingly, only the second tungsten layer remains in the contact hole or the via hole in which the barrier layer is formed, thereby forming the contact plug or the metal wiring in the contact plug or the via hole.
However, the above conventional process for forming the contact plug and the metal wiring has a problem in that the first tungsten layer is removed from the insulation interlayer simultaneously with the second tungsten layer in the planarization process. Therefore, there is a problem in that the contact hole or the via hole may not be sufficiently filled with the plug and the plug may be spaced apart from the inner surface of the hole by a distance.
FIGS. 1A to 1D are scanning electron microscope (SEM) pictures showing a wafer on which a plug structure is formed through a conventional process, as described above. FIGS. 1A and 1B are SEM pictures showing a peripheral portion of the wafer including the plug structure, and FIGS. 1C and 1D are SEM pictures showing a front face of the wafer including the plug structure. FIGS. 1A and 1C are SEM pictures showing a contact plug on the wafer and FIGS. 1B and 1D are SEM pictures showing a metal wiring on the wafer.
Referring to FIGS. 1A to 1D, a bright portion is detected around the contact plug and the metal wiring, which indicates the contact hole and the via hole are not completely filled with the plug structure and the plug structure is spaced apart from the inner surface of the contact hole and the via hole. For that reason, the bright portion around the contact plug and the metal wiring is called a defect area D. The first tungsten layer is removed from the insulation interlayer at an upper portion of the contact hole or the via hole in the planarization process to the second tungsten layer for forming the plug structure, so that the plug structure is spaced apart from an upper portion of the inner surface of the hole by a gap distance corresponding to a thickness of the first tungsten layer. Therefore, the hole is not completely filled with the plug structure, and a void is generated between the plug structure and the upper portion of the inner surface of the hole. The void between the plug structure and the upper portion of the inner surface of the hole is represented as the bright portion in the above SEM pictures which is designated as the defective area D. The defective area D is also detected between a metal wiring and an upper portion of a trench.
In order to determine whether processing defects in the defective area D are caused by the loss of the first tungsten layer or the loss of the tungsten nitride layer as well as the first tungsten layer, a sample metal wiring is formed in such a configuration so that the inner surface of the via hole is coated by only the tungsten nitride layer and the sample metal layer is measured by an SEM device.
FIG. 2A is an SEM picture showing a metal wiring of a first sample wafer in which a barrier layer for the metal wiring only includes a tungsten nitride layer, and FIG. 2B is an SEM picture showing a metal wiring of a second sample wafer in which a barrier layer for the metal wiring includes a tungsten layer and a tungsten nitride layer.
As shown in FIG. 2A, the same defective area D as shown in FIGS. 1A to 1D was not measured in case where only the tungsten nitride layer was coated on the inner surface of the via hole as the barrier layer of the metal wiring. In contrast, when the first tungsten layer was coated on the inner surface of the via hole, the defective area D was measured, as shown in FIG. 2B. Accordingly, FIGS. 2A and 2B indicate that the first tungsten layer is only removed from the insulation interlayer in the planarization process for forming the contact plug or the metal wiring, and the tungsten nitride layer has a sufficient etch resistance in the above planarization process.
However, the electrical resistance of the tungsten nitride layer functioning as the anti-diffusion layer is much greater than that of the second tungsten layer functioning as the metal wiring, so that replacement of the first tungsten layer by the tungsten nitride layer rapidly increases the electrical resistance of the contact plug or the metal wiring. Particularly, when the first tungsten layer is removed from a bottom of the contact hole or the via hole at which the plug structure makes contact with the silicon substrate, the contact resistance between the silicon substrate and the contact plug can be significantly increased, thereby causing electrical shorts and device failures.
Accordingly, there is still a need for an improved wiring structure for preventing the first tungsten layer from being removed from the substrate at an upper portion of the contact hole when the first tungsten layer still remains at the bottom of the contact hole.